(1) Field of the Invention
The invention relates to a method of metallization in the fabrication of integrated circuits, and more particularly, to a method avoiding post-etch cleaning of vias and trenches by converting etch residue to an inert layer in the manufacture of integrated circuits.
(2) Description of the Prior Art
As device geometry shrinks, it becomes more and more difficult to remove the post-etch polymer from deep submicron vias and trenches. The residue remaining in vias and trenches will affect the subsequent barrier deposition and metallization causing via poisoning, high contact/line resistance, and reliability issues. The small geometry vias and trenches also cause difficulty in metallization because too thin a barrier may lead to leakage and copper diffusion while too thick a barrier may cause a problem in gap-filling. In the case of organic low dielectric constant or porous low dielectric constant material""s being used as dielectric materials, the post-etch cleaning (polymer and copper) is a challenge for both wet and dry cleaning processes. It would be desirable to avoid the necessity for cleaning the post-etch residue from deep submicron vias and trenches and, at the same time, provide a more robust diffusion barrier.
U.S. Pat. No. 5,824,234 to Jou et al teaches a method of removing a fluorocarbon polymer from a via. U.S. Pat. No. 5,970,373 to Allen shows a method of removing a polymer within an opening. U.S. Pat. No. 5,985,762 to Geffken et al describes a barrier layer on the sidewalls of a via. The barrier layer may comprise silicon nitride or a metal or metal nitride.
A principal object of the present invention is to provide an effective and very manufacturable method of metallization without requiring post-etch cleaning in the fabrication of integrated circuit devices.
Another object of the invention is to provide a dual damascene copper metallization process without post-etch cleaning in the fabrication of an integrated circuit device.
Yet another object of the invention is to provide a dual damascene copper metallization process without post-etch cleaning wherein etch residue is converted to an inert layer.
A further object of the invention is to provide a dual damascene copper metallization process without post-etch cleaning wherein etch residue is exposed to a fluorinating agent and converted to an inert layer.
In accordance with the objects of this invention a new method to avoid post-etch cleaning in a metallization process is achieved. An insulating layer is formed over a first metal line in a dielectric layer overlying a semiconductor substrate. A via opening is etched through the insulating layer to the first metal line whereby a polymer forms on sidewalls of the via opening. The polymer is treated with a fluorinating agent whereby the polymer is converted to an inert layer. Thereafter, a second metal line is formed within the via opening wherein the inert layer acts as a barrier layer to complete the metallization process in the fabrication of an integrated circuit device.